Contents filter
| File | Package | Branch | Repository | Architecture |
|---|---|---|---|---|
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32-0.0.post106.dist-info/METADATA | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32-0.0.post106.dist-info/RECORD | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32-0.0.post106.dist-info/WHEEL | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32-0.0.post106.dist-info/top_level.txt | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/__init__.py | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/LICENSE.LATTICE | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/README | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/doc/Makefile | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/doc/mmu.rst | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/jtag_cores.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/jtag_tap_spartan6.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_adder.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_addsub.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_config.v.sample | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_cpu.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_dcache.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_debug.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_decoder.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_dp_ram.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_dtlb.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_icache.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_include.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_instruction_unit.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_interrupt.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_itlb.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_jtag.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_load_store_unit.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_logic_op.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_mc_arithmetic.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_multiplier.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_ram.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_shifter.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/rtl/lm32_top.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/.gitignore | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/Makefile | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/crt.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/hello_world.c | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/linker.ld | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/lm32_config.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/pipe1.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/tb_lm32_system.v | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/.gitignore | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/Makefile | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/crt.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/linker.ld | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/macros.inc | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/test_add.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/test_addi.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/test_and.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_lm32/verilog/test/unittests/test_andhi.S | py3-litex-hub-pythondata-cpu-lm32 | edge | testing | aarch64 |