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/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/Makefile py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/README py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/asmcheck.py py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/config.py py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/riscv-isa-sim-notrap.diff py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/riscv-isa-sim-sbreak.diff py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/riscv-torture-genloop.diff py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/riscv-torture-rv32.diff py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/riscv_test.h py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/sections.lds py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/test.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/testbench.cc py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/torture/testbench.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/.gitignore py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/Makefile py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/firmware.S py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/firmware.c py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/firmware.lds py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area.xdc py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area_large.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area_regular.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area_small.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_area_top.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_speed.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_speed.xdc py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_system.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/synth_system.xdc py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/system.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/system_tb.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/table.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/tabtest.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/vivado/tabtest.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/README.md py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/lse.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/synplify.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/vivado.tcl py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/yosys_ice40.ys py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys-cmp/yosys_xilinx.ys py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/.gitignore py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/synth_gates.lib py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/synth_gates.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/synth_gates.ys py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/synth_osu018.sh py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/scripts/yosys/synth_sim.ys py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/shell.nix py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/showtrace.py py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/testbench.cc py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/testbench.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_picorv32/verilog/testbench_ez.v py3-litex-hub-pythondata-cpu-picorv32 edge testing x86_64