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/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax.py py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim/util/vendor/google_verible_verilog_syntax_py/verible_verilog_syntax_test.py py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_gating.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_clock_mux2.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_flash.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_otp.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_pad_wrapper.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_1p.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_ram_2p.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.vlt py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/lint/prim_generic_rom.waiver py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_buf.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_buf.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_gating.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_inv.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_clock_mux2.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flash.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_2sync.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_flop_en.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_otp.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_attr.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_pad_wrapper.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_1p.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_ram_2p.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_rom.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_usb_diff_rx.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/prim_generic_xor2.core py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_buf.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_inv.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flash_bank.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_2sync.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop_en.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_otp.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_attr.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_ibex/system_verilog/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv py3-litex-hub-pythondata-cpu-ibex edge testing aarch64