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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/ex_stage.md py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
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/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/requirements.txt py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/init_testharness.do py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64
/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py py3-litex-hub-pythondata-cpu-cva6 edge testing aarch64