Contents filter
File | Package | Branch | Repository | Architecture |
---|---|---|---|---|
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7053.dist-info/METADATA | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7053.dist-info/RECORD | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7053.dist-info/WHEEL | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7053.dist-info/top_level.txt | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/__init__.py | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/.gitignore | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/README.md | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/_upstream.rev | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v | py3-litex-hub-pythondata-cpu-rocket | edge | testing | x86_64 |