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/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino-0.0.post209.dist-info/LICENSE py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino-0.0.post209.dist-info/METADATA py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino-0.0.post209.dist-info/RECORD py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino-0.0.post209.dist-info/WHEEL py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino-0.0.post209.dist-info/top_level.txt py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/__init__.py py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/.travis.yml py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/.travis/run-or1k-tests.sh py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/.travis/run-verilator.sh py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/.travis/test.sh py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/Jenkinsfile py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/LICENSE py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/README.md py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/bench/verilog/or1k_marocchino_monitor.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/bench/verilog/or1k_marocchino_traceport_monitor.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/doc/readme/fp_comparisons_table.odt py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/doc/readme/marrochino_1_goal.txt py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/doc/readme/marrochino_2_status.txt py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/doc/readme/marrochino_3_how_to.txt py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/or1k_marocchino.core py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_cfgrs.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_defines.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_dpram_en_w1st.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_bus_if_wb32.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_cache_lru.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_cpu.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_ctrl.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_dcache.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_decode.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_dmmu.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_fetch.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_icache.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_immu.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_int_1clk.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_int_div.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_int_mul.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_lsu.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_ocb.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_oman.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_pic.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_rat_cell.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_rf.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_rsrvs.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_ticktimer.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_spram_en_w1st.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_sprs.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_utils.vh py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino/pfpu_marocchino_addsub.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino/pfpu_marocchino_cmp.v py3-litex-hub-pythondata-cpu-marocchino edge testing x86_64