Contents filter
| File | Package | Branch | Repository | Architecture |
|---|---|---|---|---|
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5-0.0.post649.dist-info/LICENSE | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5-0.0.post649.dist-info/METADATA | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5-0.0.post649.dist-info/RECORD | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5-0.0.post649.dist-info/WHEEL | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5-0.0.post649.dist-info/top_level.txt | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/__init__.py | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/.gitlab-ci.yml | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/LICENSE | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/README.md | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/addr_hash.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/alu_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/amo_alu.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/avalon_master.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/axi_master.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/axi_to_arb.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/barrel_shifter.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/binary_occupancy.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_comparator.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_predictor.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_predictor_ram.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/branch_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/byte_en_BRAM.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/clz.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/csr_types.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/csr_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_config.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_fifo.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/cva5_types.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/cycler.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/dcache.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/ddata_bank.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/decode_and_issue.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/div_core.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/div_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/dtag_banks.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/external_interfaces.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/fetch.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/gc_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/icache.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/illegal_instruction_checker.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/instruction_metadata_and_id_management.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/intel/intel_byte_enable_ram.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/interfaces.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/itag_banks.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/l1_arbiter.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/lfsr.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/load_store_queue.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/load_store_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |
| /usr/lib/python3.12/site-packages/pythondata_cpu_cva5/system_verilog/core/local_mem_sub_unit.sv | py3-litex-hub-pythondata-cpu-cva5 | edge | testing | x86_64 |