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/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_popcnt.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_buffer.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_controller.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_ff.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_latch.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_sleep_unit.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_apu_core_pkg.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_fpu_pkg.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_pkg.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/README.md py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_cmp.csh py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_conformal.sh py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/src_files.yml py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/sva/cv32e41p_prefetch_controller_sva.sv py3-litex-hub-pythondata-cpu-cv32e41p edge testing x86_64