Contents filter
File | Package | Branch | Repository | Architecture |
---|---|---|---|---|
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/Makefile | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/README.md | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/amo_shim.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/crt0.S | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/hello_world.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/link.ld | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/syscalls.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/vectors.S | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/main.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/matmulNxN.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_fp_wrapper.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_random_interrupt_generator.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_tb_subsystem.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/dp_ram.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware/stats.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp.h | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp_test.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include/perturbation_pkg.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/interrupt.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/isr.h | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/matrix.h | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/vectors.S | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.c | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.h | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mm_ram.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_gnt_stall.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_rvalid_stall.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/software.tcl | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/tb_top.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/vsim.tcl | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/waves.tcl | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts/pulptrace | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_aligner.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu_div.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_apu_disp.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_controller.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_core.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_cs_registers.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ex_stage.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ff_one.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_fifo.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_hwloop_regs.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_id_stage.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_if_stage.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_int_controller.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_load_store_unit.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_merged_decoder.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_mult.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_obi_interface.sv | py3-litex-hub-pythondata-cpu-cv32e41p | edge | testing | x86_64 |