Contents filter
File | Package | Branch | Repository | Architecture |
---|---|---|---|---|
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/fpnew/src/fpu_div_sqrt_mvp/src_files.yml | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/fpnew/src_files.yml | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_core_package.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include/apu_macros.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_config.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_defines.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/include/riscv_tracer_defines.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/register_file_test_wrap.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/.travis.yml | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/Bender.yml | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/CHANGELOG.md | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/LICENSE | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/LICENSE.SiFive | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/README.md | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/download-pulp-gcc.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/get-openocd.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/install-verilator.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/make-tmp.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/openocd-to-junit.py | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/run-openocd-compliance.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/ci/veri-run-openocd-compliance.sh | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/.gitignore | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/Makefile | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/debug_rom.S | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/debug_rom.h | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/debug_rom.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/encoding.h | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/gen_rom.py | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/debug_rom/link.ld | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/doc/debug-system.md | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/doc/debugsys_schematic.svg | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/doc/dmi_protocol.json | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/doc/dmi_protocol.svg | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_csrs.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_mem.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_pkg.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_sba.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_top.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dm_wrap.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dmi_cdc.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dmi_jtag.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src/dmi_jtag_tap.sv | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/src_files.yml | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/tb/.clang-format | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/tb/.gitignore | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/tb/LICENSE.Berkeley | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |
/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e40p/system_verilog/rtl/riscv-dbg/tb/LICENSE.SiFive | py3-litex-hub-pythondata-cpu-cv32e40p | edge | testing | x86_64 |